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XCR3064XL 64 Macrocell CPLD
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DS017 (v1.6) January 8, 2002
Product Specification
Features
* * * * * Lowest power 64 macrocell CPLD 6.0 ns pin-to-pin logic delays System frequencies up to 145 MHz 64 macrocells with 1,500 usable gates Available in small footprint packages * * 44-pin PLCC (36 user I/O pins) 44-pin VQFP (36 user I/O pins) 48-ball CS BGA (40 user I/O pins) 56-ball CP BGA (48 user I/O pins) 100-pin VQFP (68 user I/O pins) Ultra-low power operation 5V tolerant I/O pins with 3.3V core supply Advanced 0.35 micron five layer metal EEPROM process Fast Zero PowerTM (FZP) CMOS design technology In-system programming Predictable timing model Up to 23 available clocks per function block Excellent pin retention during design changes Full IEEE Standard 1149.1 boundary-scan (JTAG) Four global clocks Eight product term control terms per function block
Description
The XCR3064XL is a 3.3V, 64-macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of four function blocks provide 1,500 usable gates. Pin-to-pin propagation delays are 6.0 ns with a maximum system frequency of 145 MHz.
TotalCMOS Design Technique for Fast Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technology and design technique. Xilinx employs a cascade of CMOS gates to implement its sum of products instead of the traditional sense amp approach. This CMOS gate implementation allows Xilinx to offer CPLDs that are both high performance and low power, breaking the paradigm that to have low power, you must have low performance. Refer to Figure 1 and Table 1 showing the ICC vs. Frequency of our XCR3064XL TotalCMOS CPLD (data taken with four resetable up/down, 16-bit counters at 3.3V, 25C).
35.0 30.0
Optimized for 3.3V systems
Advanced system features Input registers
Typical ICC (mA)
25.0 20.0 15.0 10.0 5.0 0.0 0 20 40 60 80 100 120 140
* * * * * *
Fast ISP programming times Port Enable pin for dual function of JTAG ISP pins 2.7V to 3.6V supply voltage at industrial temperature range Programmable slew rate control per macrocell Security bit prevents unauthorized access Refer to XPLA3 family data sheet (DS012) for architecture description
Frequency (MHz)
DS017_01_102401
Figure 1: ICC vs. Frequency at VCC = 3.3V, 25C
Table 1: ICC vs. Frequency (VCC = 3.3V, 25C) Frequency (MHz) Typical ICC (mA) 0 0 1 0.2 5 1.0 10 2.0 20 3.9 40 7.6 60 11.3 80 14.8 100 18.5 120 22.1 140 25.6
(c) 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS017 (v1.6) January 8, 2002 Product Specification
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DC Electrical Characteristics Over Recommended Operating Conditions(1)
Symbol VOH(2) VOL IIL IIH ICCSB ICC Parameter Output High voltage Output Low voltage for 3.3V outputs Input leakage current I/O High-Z leakage current Standby current Dynamic current(3,4) Test Conditions IOH = -8 mA IOL = 8 mA VIN = GND or VCC VIN = GND or VCC VCC = 3.6V f = 1 MHz f = 50 MHz CIN CCLK CI/O Input pin capacitance(5) Clock input capacitance(5) I/O pin capacitance (5) f = 1 MHz f = 1 MHz f = 1 MHz Min. 2.4 -10 -10 Max. 0.4 10 10 100 0.5 15 8 12 10 Unit V V A A A mA mA pF pF pF
Notes: 1. See XPLA3 family data sheet (DS012) for recommended operating conditions. 2. See Figure 2 for output drive characteristics of the XPLA3 family. 3. See Table 1, Figure 1 for typical values. 4. This parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and unloaded. Inputs are tied to V CC or ground. This parameter guaranteed by design and characterization, not testing. 5. Typical values, not tested.
100 90 80 70 60 IOL (3.3V)
mA
50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 IOH (2.7V) IOH (3.3V)
Volts
DS012_10_041901
Figure 2: Typical I/V Curve for the XPLA3 Family
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DS017 (v1.6) January 8, 2002 Product Specification
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XCR3064XL 64 Macrocell CPLD
AC Electrical Characteristics Over Recommended Operating Conditions(1,2)
-6 Symbol TPD1 TPD2 TCO TSUF TSU1 TSU2 TH
(4) (4) (4)
-7 Max. 5.5 6.0 4.0 20 20 145 60 60 7.5 7.5 6.5 8.0 Min. 2.5 4.3 4.8 0 3.0 5.0 Max. 7.0 7.5 5.0 20 20 119 60 60 9.3 9.3 8.3 9.3 Min. 3.0 5.4 6.3 0 4.0 6.0 -
-10 Max. 9.1 10.0 6.5 20 20 95 60 60 11.2 11.2 10.7 11.2 Unit ns ns ns ns ns ns ns ns ns ns ns MHz s s ns ns ns ns
Parameter Propagation delay time (single p-term) Propagation delay time (OR array)(3) Clock to output (global synchronous pin clock) Setup time (fast input register) Setup time (single p-term) Setup time (OR array) Hold time Global Clock pulse width (High or Low) P-term clock pulse width Input rise time Input fall time
Min. 2.5 3.5 4.0 0 2.5 4.0 -
TWLH TR(4) TL(4)
TtPLH(4)
fSYSTEM TINIT(4) TPOE(4) TPOD(4) TPCO(4) TPAO (4)
(4) (4)
Maximum system frequency Configuration time(5) ISP initialization time P-term OE to output enabled P-term OE to output disabled(6) P-term clock to output P-term set/reset to output valid
TCONFIG
Notes: 1. Specifications measured with one output switching. 2. See XPLA3 family data sheet (DS012) for recommended operating conditions. 3. See Figure 4 for derating. 4. These parameters guaranteed by design and/or characterization, not testing. 5. Typical current draw during configuration is 6 mA at 3.6V. 6. Output CL = 5 pF.
DS017 (v1.6) January 8, 2002 Product Specification
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Internal Timing Parameters(2)
-6 Symbol Buffer Delays TIN TFIN TGCK TOUT TEN Input buffer delay Fast Input buffer delay Global Clock buffer delay Output buffer delay Output buffer enable/disable delay 1.3 2.3 0.8 2.2 4.2 1.6 3.0 1.0 2.7 5.0 2.2 3.1 1.3 3.6 5.7 ns ns ns ns ns Parameter Min. Max. Min. -7 Max. Min. -10 Max. Unit
Internal Register and Combinatorial Delays TLDI TSUI THI TECSU TECHO TCOI TAOI TRAI TLOGI1 TLOGI2 Latch transparent delay Register setup time Register hold time Register clock enable setup time Register clock enable hold time Register clock to output delay Register async. S/R to output delay Register async. recovery Internal logic delay (single p-term) Internal logic delay (PLA OR term) 1.0 0.3 2.0 3.0 1.3 1.0 2.5 4.0 2.0 2.5 1.0 0.5 2.5 4.5 1.6 1.3 2.3 5.0 2.7 3.2 1.2 0.7 3.0 5.5 2.0 1.6 2.1 6.0 3.3 4.2 ns ns ns ns ns ns ns ns ns
Feedback Delays TF ZIA delay 2.4 2.9 3.5 ns
Time Adders TLOGI3 TUDA TSLEW Fold-back NAND delay Universal delay Slew rate limited delay 6.0 1.5 4.0 7.5 2.0 5.0 9.5 2.5 6.0 ns ns ns
Notes: 1. These parameters guaranteed by design and/or characterization, not testing. 2. See XPLA3 family data sheet (DS012) for timing model.
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DS017 (v1.6) January 8, 2002 Product Specification
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XCR3064XL 64 Macrocell CPLD
Switching Characteristics
VCC
S1 Component R1 R2 C1 VOUT R2 C1 Values 390 390 35 pF
R1 VIN
Measurement TPOE (High) TPOE (Low) TP
S1 Open Closed Closed
S2 Closed Open Closed
S2
Note: For TPOD, C1 = 5 pF. Delay measured at output level of VOL + 300 mV, VOH - 300 mV.
DS017_03_102401
Figure 3: AC Load Circuit
5.6 5.5 5.4
+3.0V 90%
10% 0V
(ns)
5.3 5.2
TR
1.5 ns
TL
1.5 ns
5.1 5.0 4.9 1 2 4 8 16
Measurements: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified.
DS017_05_042800
Number of Adjacent Outputs Switching
DS017_04_042800
Figure 5: Voltage Waveform
Figure 4: Derating Curve for TPD2
DS017 (v1.6) January 8, 2002 Product Specification
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Pin Descriptions
Table 2: XCR3064XL User I/O Pins PC44 Total User I/O Pins 36 VQ44 36 CS48 40 CP56 48 VQ100 68
Table 3: XCR3064XL I/O Pins Function MacroBlock cell PC44 VQ44 CS48 CP56 VQ100 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
Notes: 1. JTAG pins
15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
12 32(1) 31 29 28 27 26 25 24 13(1) 14 16 17 18 19 20 21 -
6 26(1) 25 23 22 21 20 19 18 7(1) 8 10 11 12 13 14 15 -
D1 E5(1) E7 F7 F6 G7 G6 F5 G5 F4 D2(1) E1 F1 G1 E4 F2 G2 F3 G3 -
F1 F10(1) G8 H10 K8 K10 K9 J10 H8 H7 H6 K7 G1(1) F3 G3 J1 K1 K4 K2 K3 H3 H4 K5 -
13 14 62(1) 61 60 58 57 56 54 52 48 47 46 45 44 42 41 40 15(1) 16 17 19 20 21 23 25 29 30 31 32 33 35 36 37
Table 3: XCR3064XL I/O Pins Function MacroBlock cell PC44 VQ44 CS48 CP56 VQ100 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 41 40 39 38(1) 37 36 34 33 4 5 6 7(1) 8 9 11 35 34 33 32(1) 31 30 28 27 42 43 44 1(1) 2 3 5 C5 A6 A7 B6 B7(1) D4 C6 D6 D7 A2 A1 C4 B2 B1(1) C2 C1 D3 C8 A8 A9 A5 A10 B10 C10(1) D8 E8 F8 E10 C4 C3 A1 B1 A2 A3 C1(1) D1 D3 E3 85 84 83 81 80 79 76 75 73(1) 71 69 68 67 65 64 63 92 93 94 96 97 98 99 100 4(1) 6 8 9 10 12
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DS017 (v1.6) January 8, 2002 Product Specification
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XCR3064XL 64 Macrocell CPLD
Table 4: XCR3064XL Global, JTAG, Port Enable, Power, and No connect Pins Pin Type IN0 / CLK0 IN1 / CLK1 IN2 / CLK2 IN3 / CLK3 TCK TDI TDO TMS PORT_EN VCC GND No Connects PC44 2 1 44 43 32 7 38 13 10(1) 3, 15, 23, 35 22, 30, 42 VQ44 40 39 38 37 26 1 32 7 4(1) 9, 17, 29, 41 16, 24, 36 CS48 A3 B4 A4 B5 E5 B1 B7 D2 C3(1) B3, C7, E2, G4 A5, E3, E6 CP56 C5 C6 C7 A6 F10 C1 C10 G1 E1(1) A4, D10, H1, H5 A7, G10, K6 VQ100 90 89 88 87 62 4 73 15 11(1) 3, 18, 34, 39, 51, 66, 82, 91 26, 38, 43, 59, 74, 86, 95 1, 2, 5, 7, 22, 24, 27, 28, 49, 50, 53, 55, 70, 72, 77, 78
Notes: 1. Port Enable is brought High to enable JTAG pins when JTAG pins are used as I/O. See family data sheet (DS012) for more information.
DS017 (v1.6) January 8, 2002 Product Specification
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Ordering Information
Example:
Device Type Speed Grade
XCR3064XL -7 VQ 44 C
Temperature Range Number of Pins Package Type
Device Ordering Options
Speed -10 -7 -6 10 ns pin-to-pin delay 7.5 ns pin-to-pin delay 6 ns pin-to-pin delay PC44 VQ44 CS48 CP56 VQ100 Package 44-pin Plastic Leaded Chip Carrier 44-pin Very Thin Quad Flat Pack 48-ball Chip Scale Package 56-ball Chip Scale Package 100-pin Very Thin Quad Flat Package Temperature C = Commercial I = Industrial TA = 0C to + 70C VCC = 3.0V to 3.6V TA = -40C to + 85C VCC = 2.7V to 3.6V
Component Availability
Pins Type Code XCR3064XL -6 -7, -10 100 Plastic VQFP VQ100 C C,I 56 Plastic BGA CP56 C C,I 48 Plastic BGA CS48 C C,I 44 Plastic VQFP VQ44 C C,I 44 Plastic PLCC PC44 C C,I
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DS017 (v1.6) January 8, 2002 Product Specification
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XCR3064XL 64 Macrocell CPLD
Revision History
The following table shows the revision history for this document.. Date 06/01/00 08/30/00 11/18/00 12/08/00 04/11/01 04/19/01 01/08/02 Version 1.0 1.1 1.2 1.3 1.4 1.5 1.6 Initial Xilinx release. Added 48-ball CS BGA package. Updated to full production data sheet; corrected note in Table 4 to read: "port enable pin is brought High". Added PC44 package. Added Typical I/V curve, Figure 2; added Table 2: Total User I/O; changed VOH spec. Updated Typical I/V curve, Figure 2: added voltage levels. Moved ICC vs. Freq Figure 1 and Table 1 to page 1. Added single p-term setup time (TSU1) to AC Table, renamed TSU to TSU2 for setup time through the OR array. Updated TSUF and TFIN spec to match software timing. Added TINIT spec. Updated TCONFIG spec. Updated THI spec to correct a typo. Updated AC Load Circuit diagram to more closely resemble true test conditions, added note for TPOD delay measurement. Updated note 5 in AC Characteristics table lowering typical current draw during configuration. Revision
DS017 (v1.6) January 8, 2002 Product Specification
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